1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to an element isolation structure of a semiconductor device and a method of manufacturing the same.
2. Description of the Background Art
Conventionally, LOCOS (Local Oxidation of Silicon) is widely known as a method for providing isolation between elements. FIGS. 47 and 48 are cross sectional views showing the process flow in the case in which this LOCOS method is employed in a semiconductor device having an SOI (Semiconductor On Insulator) structure.
Referring first to FIG. 47, a semiconductor layer (hereinafter simply referred to as xe2x80x9cSOI layerxe2x80x9d) 3 is formed on a main surface of a silicon substrate 1 with a buried oxide layer 2 therebetween, using SIMOX (Separation by Implanted Oxygen) method or the like. On this SOI layer 3, a nitride layer 11 patterned to obtain a prescribed shape is formed. Using this nitride layer 11 as a mask, ions of boron (B) are implanted to SOI layer 3. As a result, an impurity implantation region 4a which is to be a channel stopper region is formed.
Thereafter, LOCOS processing is performed on SOI layer 3 in a state as shown in FIG. 47. This forms an isolation oxide layer 20 selectively at SOI layer 3 as shown in FIG. 48. At this time, owing to the formation of isolation oxide layer 20, most of the impurity (boron) for forming the channel stopper region mentioned above is absorbed. Accordingly, ion implantation of boron (B) has to take place again in the vicinity of the edge portion of SOI layer 3 after isolating oxide film 20 is formed, thereby forming a channel stopper region 4 including an impurity (boron) of high concentration in the vicinity of the edge portion of SOI layer 3. As a result, it is made possible to effectively suppress the decrease of threshold voltage Vth of a parasitic MOS transistor in the vicinity of the edge portion of SOI layer 3.
However, when ion implantation of boron for forming channel stopper region 4 is performed after isolation oxide layer 20 is formed, there has been a problem as described in the following.
As shown in FIG. 48, one way to form channel stopper region 4 after the formation of isolation oxide layer 20 is to implant ions of boron selectively into the vicinity of the edge portion of SOI layer 3 only, with nitride layer 11 still remaining. Since this method enables channel stopper region 4 to be formed in a self-aligned manner, there is no need to form a new mask layer for ion implantation of boron described above. However, as shown in FIG. 48, implantation of boron ions by oblique ion implantation method is required in the vicinity of edge portion of SOI layer 3. Therefore, the above-described boron would be implanted to the region where the channel of MOS transistor is formed. As a result, there has been a problem that the effective channel width W would be small.
One method by which the problem as described above can be solved is a mesa isolation method shown in FIGS. 49 to 51. FIG. 49 is a cross-sectional view showing a semiconductor device in which a conventional mesa isolation method is adopted. FIGS. 50 and 51 are cross-sectional views showing the manufacturing process which is characteristic in the semiconductor device of FIG. 49.
Referring first to FIG. 49, a channel stopper region 4 is formed in the vicinity of the edge portion of an SOI layer 3. A recess portion 24 is formed directly under the edge portion of SOI layer 3. A gate insulation layer 7 is formed to cover SOI layer 3, and a gate electrode 8 is formed to cover this gate insulation layer 7.
Referring next to FIGS. 50 and 51, a method of manufacturing the semiconductor device shown in FIG. 49 will now be described. Referring first to FIG. 50, ion implantation of boron (B) for forming channel stopper region 4 is performed to SOI layer 3 by a method similar to the example of the above-described LOCOS. Thereafter, a nitride layer (not shown) is additionally formed to cover nitride layer 11, using CVD (Chemical Vapor Deposition). Then, by performing an anisotropical etching to the nitride layer, a nitride spacer 12 is formed as shown in FIG. 51. Thereafter, using nitride layer 11 and nitride spacer 12 as a mask, SOI layer 3 is patterned, followed by thermal oxidation for eliminating etching damages. Thus, a sidewall oxide layer 5 is formed at the sidewall of SOI layer 3, as shown in FIG. 51.
Thereafter, nitride layer 11, nitride spacer 12 and oxide layer 9 are removed by etching. As a result, recess portion 24 is formed directly beneath the edge portion of SOI layer 3.
Thereafter, gate insulation layer 7 is formed on the surface of SOI layer 3, and a gate electrode 8 is formed so as to cover this gate insulation layer 7. Then, in this case, source/drain regions are formed so as to sandwich the gate electrode 8 in SOI layer 3.
By the process as described above, a semiconductor device shown in FIG. 49 is formed. In this semiconductor device shown in FIG. 49, boron (B) for forming channel stopper region 4 is not implanted for the second time as in the case where the LOCOS method is adopted. Accordingly, the problem of small effective channel width W in the case where LOCOS is adopted can be solved.
However, even in the semiconductor device shown in FIG. 49, there has been a problem as described in the following. As shown in FIG. 51, sidewall oxide layer 5 is formed after the formation of channel stopper region 4. At this time, the impurity (boron) could be drawn out from channel stopper region 4 due to the formation of this sidewall oxide layer 5, although not as much as in the case of the above-described LOCOS method. Accordingly, concentration of the impurity (boron) within channel stopper region 4 is reduced, thus leading to a problem that threshold voltage Vth of the parasitic MOS transistor at the edge portion of SOI layer 3 is lowered. In addition, as shown in FIG. 49, recess portion 24 is formed directly beneath the edge portion of SOI layer 3. With such recess portion 24 formed, concentration of electric field is likely at the sidewall bottom portion 26 of SOI layer 3. This also leads to increase in the possibility of insulation breakdown, thus lowering the yield of the transistor.
The present invention was made to solve the problems as described above. It is one object of the present invention to provide a semiconductor device in which effective suppression of decrease in the threshold voltage Vth of a parasitic MOS transistor at an edge portion of an SOI layer is possible, and a method of manufacturing the same.
It is another object of the present invention to provide a semiconductor device in which effective suppression of insulation breakdown of a gate insulation layer is possible.
It is assumed that the semiconductor device according to the present invention has an SOI (Semiconductor on Insulator) structure. The semiconductor device according to the present invention includes a semiconductor substrate having a main surface, a mesa type semiconductor layer isolated by mesa isolation method, a channel stopper region, an isolating insulation layer, and a gate electrode. A semiconductor layer is formed on the main surface of the semiconductor substrate with a buried insulation layer therebetween, and has source/drain regions internally. The channel stopper region is formed in the vicinity of the edge portion of the semiconductor layer. The isolation insulation layer is formed on the channel stopper region and on the edge portion of the semiconductor layer, and has an upper surface on the channel stopper region inclined so as to be apart upwards from the upper surface of the semiconductor layer as it approaches the edge portion of the semiconductor layer. The gate electrode is extended from a region over the semiconductor layer to the isolating insulation layer.
As described above, in the semiconductor device according to the present invention, the isolating insulation layer is formed on the channel stopper region and on the edge portion of the semiconductor layer. By this isolating insulation layer, it is made possible to effectively prevent the formation of recess portion 24 shown in FIG. 49 directly under the edge portion of the semiconductor layer. In addition, the isolating insulation layer is also formed on the channel stopper region and has an upper surface inclined to be apart upwards from the upper surface of the semiconductor layer as it approaches the edge portion of the semiconductor layer. Since the gate electrode extends on the isolating insulation layer, it is possible to keep away the gate electrode from the edge portion of the semiconductor layer. Accordingly, it is possible to suppress decrease in the threshold voltage Vth of the parasitic MOS transistor at the edge portion of the semiconductor layer.
Preferably, the side end portion of the isolating insulation layer located on the semiconductor layer is placed closer to the edge portion of the semiconductor layer than to the inner side end portion of the channel stopper region located in the semiconductor layer. Thus, it is ensured that the inclined upper surface of the isolating insulation layer can be arranged on the region in the vicinity of the edge portion of the semiconductor layer. As a result, it is made possible to keep away the gate electrode from the edge portion of the semiconductor layer with more certainty.
Also, the above-described isolating insulation layer may include a protruded insulation layer formed on the channel stopper region and a sidewall insulation layer formed under this protruded insulation layer covering the edge portion of the semiconductor layer.
In addition, it is preferred that the above-described isolating insulation layer extends from a region over the channel stopper region to the buried insulation layer approximate the semiconductor layer, having an even upper surface adjacent to the above-described inclined upper surface. Also, the semiconductor layer preferably has a first conductive layer formed thereon with a gate insulation layer therebetween, and a second conductive layer is formed on this first conductive layer to extend over the isolating insulation layer. These first and second conductive layers form a gate electrode. It is preferred that the above-described even upper surface is positioned higher with respect to the upper surface of the semiconductor layer as compared to the upper surface of the above-described first conductive layer. In this way, the second conductive layer can be kept from the edge portion of the semiconductor layer effectively. As a result, it is made possible to effectively suppress the decrease in the threshold voltage Vth of the parasitic MOS transistor at the edge portion of the semiconductor layer.
In the method of manufacturing a semiconductor device according to the present invention, in one aspect, an SOI substrate is prepared by forming a semiconductor layer on a main surface of a semiconductor substrate with a buried insulation layer therebetween. An insulation layer is formed on this semiconductor layer, and a first masking layer is formed selectively on this insulation layer. A second masking layer of a material different from that of the first masking layer is formed selectively on the insulation layer to cover the sidewall and the upper surface of the first masking layer. Using this second masking layer as a mask, the insulation layer and the semiconductor layer are patterned. Then, using the second masking layer as a mask, the sidewall of the patterned semiconductor layer is oxidized. After removing the second masking layer, the first masking layer is used as a mask for implanting impurity to the region in the vicinity of the edge portion of the semiconductor layer which had been covered with the second masking layer, thereby forming a channel stopper region. A gate electrode is formed above the semiconductor layer. Source/drain regions are formed within the semiconductor layer.
As described above, in one aspect of the method of manufacturing the semiconductor device according to the present invention, the semiconductor layer is patterned by using the second masking layer formed to cover the sidewall and the upper surface of the first masking layer as a mask, and then this second masking layer is used as a mask to oxidize the sidewall of the semiconductor layer. After removing this second masking layer, the first masking layer is used as a mask to implant impurity for forming the channel stopper region into the region in the vicinity of the edge portion of the semiconductor layer which had been covered with the second masking layer in a self-aligned manner. Thus, absorption of the impurity for forming the channel stopper region into the oxide film formed by thermal treatment performed to the above-described sidewall of the semiconductor layer can be suppressed effectively. As a result, reduction in concentration of impurity contained in the channel stopper region can be suppressed effectively. Thus, reduction in threshold voltage Vth of the parasitic MOS transistor at the edge portion of the semiconductor layer can be suppressed effectively.
In addition, the step of forming the above-described channel stopper region preferably includes the step of performing a channel doping by implanting impurity into the semiconductor layer by the energy penetrating the first masking layer to reach the semiconductor layer. Thus, it is made also possible to perform a channel doping using the mask for forming the channel stopper region. As a result, it becomes unnecessary to form a new masking layer for channel doping such that the process can be simplified.
Also, it is preferred that the above-described first masking layer is formed of polycrystalline silicon and the second masking layer of nitride. In addition, the step of forming the gate electrode includes steps of forming a sidewall insulation layer on the sidewall of the first masking layer and the sidewall of the semiconductor layer, selectively exposing the surface of the semiconductor layer by etching away the first masking layer and the insulation layer successively, and forming the gate electrode on the surface of the exposed semiconductor layer with a gate insulation layer therebetween. By forming a sidewall insulation layer at the sidewall of the first masking layer and on the sidewall of the semiconductor layer as described above, it is made possible to keep away the gate electrode from the edge portion of the semiconductor layer upon formation of the gate electrode above the semiconductor layer, and in addition, it is also made possible to protect the edge portion of the semiconductor layer.
In addition, the above-described step of forming the gate electrode preferably includes steps of forming an isolating insulation layer on the buried insulation layer to cover the first masking layer and the channel stopper region, and removing a portion of the isolating insulation layer to expose the upper surface of the first masking layer. At this time, the first masking layer is provided so that it can function as a stopper. In this way, when a portion of the isolating insulation layer is removed by a CMP (Chemical Mechanical Polishing) process, for example, the accuracy of the polishing by the CMP process can be improved. In addition, by forming the isolating insulation layer in this way, it is also possible to protect the edge portion of the semiconductor layer by this isolating insulation layer.
The above-described step of forming the gate electrode preferably further includes the steps of exposing selectively the surface of the semiconductor layer by removing the above-described exposed first masking layer and the insulation layer, and forming a gate electrode on the exposed surface of the semiconductor layer with the gate insulation layer therebetween. By removing the first masking layer and the insulation layer in this way, it is possible to form an isolating insulation layer having a sloped surface inclining upwards as it extend toward the edge portion of the semiconductor layer on the channel stopper region. Thus, it is possible to effectively keep away the gate electrode from the edge portion of the semiconductor layer.
In addition, the above-described first masking layer is preferably formed of polycrystalline silicon, and the step of forming the gate electrode preferably further includes the steps of forming a polycrystalline silicon layer on the first masking layer to extend over the isolating insulation layer and forming a gate electrode by patterning this polycrystalline layer and the first masking layer. By thus forming the first masking layer from polycrystalline silicon, this first masking layer can be used as a portion of the gate electrode. In this case, the only step needed is to form a new polycrystalline silicon layer on the first masking layer, and thus the manufacturing process can be simplified as compared to the case in which the first masking layer has to be removed.
In addition, the above-described first masking layer may include first and second polycrystalline silicon layers, and the above-described insulation layer may include first and second insulation layers. In this case, the step of forming the first masking layer includes the steps of forming the first polycrystalline silicon layer on the semiconductor layer with a first insulation layer therebetween, and forming the second polycrystalline silicon layer on this first polycrystalline silicon layer with a second insulation layer therebetween. The second masking layer is formed to cover the first and second polycrystalline silicon layers. The step of forming the gate electrode preferably includes the steps of exposing the surface of the above-described second polycrystalline silicon layer by a process of removing a portion of the isolating insulation layer, removing this second polycrystalline silicon layer and the second insulation layer, forming a third polycrystalline silicon layer on the first polycrystalline silicon layer to be extended on the isolating insulation layer, and forming a gate electrode by patterning the third polycrystalline silicon layer and the first polycrystalline silicon layer. By thus forming the first and second polycrystalline silicon layers, the level of the upper surface of the isolating insulation layer after the process of removing a portion of the isolating insulation layer can be made higher than the level of the upper surface of the first polycrystalline silicon layer. Accordingly, the gate electrode can be kept away from the edge portion of the semiconductor layer more effectively.
The above-described step of forming the first masking layer preferably includes the step of forming a nitride layer on the above-described second polycrystalline silicon layer, and forming first and second sidewall oxide layers by using this nitride layer as a mask for oxidizing the sidewall of first and second polycrystalline silicon layers. The step of forming the second masking layer includes the step of forming the second masking layer to cover the first and second sidewall oxide layers. By thus oxidizing the edge portion of the first and second polycrystalline silicon layers, it is possible to eliminate the etching damage upon the patterning of the first and second polycrystalline silicon layers.
In accordance with the method of manufacturing the semiconductor device according to the present invention, in another aspect, an insulation layer is first formed on a main surface of a semiconductor substrate, and a first masking layer is formed selectively on this insulation layer. Covering the upper surface and the sidewall of this first masking layer, a second masking layer of a material different from that of the first masking layer is formed selectively on the insulation layer. Using this second masking layer as mask, the insulation layer and the main surface of the semiconductor substrate are subjected to etching so as to form a trench for element isolation. Using the second masking layer as a mask, inner surface of the trench is oxidized. After removing the second masking layer, the first masking layer is used as a mask to implant impurity to the inner surface of the trench and the main surface of the semiconductor substrate which was covered by the second masking layer so as to form a channel stopper region. An isolating insulation layer is formed on the main surface of the semiconductor substrate to cover the first masking layer and the trench. A portion of the isolating insulation layer is removed to expose the upper surface of the first masking layer. Then, a gate electrode is formed above the main surface of the semiconductor substrate. Source/drain regions are formed in the main surface of the semiconductor substrate to sandwich the above-described gate electrode.
As described above, after the trench is formed using the second masking layer as a mask, the second masking layer is removed, and the first masking layer is used as a mask to implant impurity to the inner surface of the trench and to the main surface of the semiconductor substrate which was covered by the second masking layer so as to form the channel stopper region. In this way, it is possible to form the channel stopper region also in the main surface of the semiconductor substrate between the side end portion of the first masking layer and the upper end corner portion of the trench. Since implantation of impurity for forming the channel stopper region is performed after the oxidation of the inner surface of the trench in this aspect also, decrease in the impurity concentration at the channel stopper region can be suppressed as in the case of the one aspect described above. Accordingly, it is possible to prevent effectively the decrease in the threshold voltage Vth of the parasitic MOS transistor.
In accordance with a method of manufacturing a semiconductor device according to the present invention, in still another aspect, an SOI (Semiconductor On Insulator) substrate is first prepared by forming a semiconductor layer on a main surface of a semiconductor substrate with a buried insulation layer therebetween. An insulation layer is formed on this semiconductor layer, and a first masking layer is formed selectively on this insulation layer. A second masking layer of a material different from that of the first masking layer is formed selectively on the insulation layer so as to cover the upper surface and the sidewall of this first masking layer. Using this second masking layer as a mask, the semiconductor layer is subjected to a selective oxidation to form an isolating oxide film. After removing the second masking layer, the first masking layer is used as a mask for implanting impurity in the vicinity of the edge portion of the semiconductor layer which was covered by the second masking layer, thereby forming a channel stopper region. A gate electrode is formed above the semiconductor layer. Source/drain regions are formed in the semiconductor layer, sandwiching this gate electrode.
As described above, in this aspect, the second masking layer is used as a mask for forming the isolating oxide film, the second masking layer is then removed, and thereafter, the first masking layer is used as a mask to implant impurity in the vicinity of the edge portion of the semiconductor layer which was covered by the second masking layer so as to form the channel stopper region. In this way, the channel stopper region can be formed in the vicinity of the edge portion of the semiconductor layer in the self-aligned manner with certainty, and in addition, it is made possible to prevent effectively the absorption of the impurity from the channel stopper region owing to the formation of isolating oxide film. Thus, it is ensured that channel stopper region including impurity of high concentration can be formed at the edge portion of the semiconductor layer. As a result, decrease in the threshold voltage Vth of parasitic MOS transistor at the edge portion of the semiconductor layer can be suppressed effectively.
The above-described step of forming the isolating oxide film may include the steps of forming an oxide layer having a bottom surface in the semiconductor layer by selectively oxidizing the semiconductor layer using the second masking layer as mask, forming a nitride layer after removing this oxide layer to cover the semiconductor layer and a second masking layer, performing anisotropical etching to this nitride layer such that the nitride layer is left under the second masking layer, and forming the isolating oxide film by selectively oxidizing the semiconductor layer using the second masking layer and the nitride layer as a mask. By forming the isolating oxide film through a process as described above, the slope of the side surface of the semiconductor layer can be made steep. Accordingly, partial reduction in the film thickness at the edge portion of the semiconductor layer can be suppressed effectively. Thus, formation of a parasitic MOS transistor with a low threshold voltage Vth at the edge portion of the semiconductor layer can be suppressed effectively.
The above-described first masking layer is preferably formed of polycrystalline silicon. The step of forming the gate electrode preferably includes the steps of forming a polycrystalline silicon layer on the first masking layer and on the isolating oxide film, and forming the gate electrode by patterning this polycrystalline silicon layer and the first masking layer. As a result, manufacturing process can be simplified as compared to the case in which the first masking layer is removed.
In accordance with a method of manufacturing a semiconductor device according to the present invention, in still another aspect, an SOI (Semiconductor On Insulator) substrate is prepared by forming a semiconductor layer on a main surface of a semiconductor substrate with a buried insulation layer therebetween. A first masking layer is formed on this semiconductor layer with an insulation layer therebetween. On this first masking layer, a second masking layer of a material different from that of the first masking layer is formed. After patterning the second masking layer, this second masking layer is used as a mask to implant impurity for forming a channel stopper region in the semiconductor layer. A third masking layer of a material which is the same as that of the second masking layer is formed on the sidewall of the second masking layer. Thereafter, using these second and third masking layers as a mask, the first masking layer, the insulation layer and the semiconductor layer are patterned successively. After removing the second and third masking layers, a sidewall insulation layer is formed on the sidewall of the semiconductor layer. By etching away the first masking layer and the insulation layer, the surface of the semiconductor layer is exposed. A gate electrode is formed on the surface of the semiconductor layer with a gate insulation layer therebetween. Source/drain regions are formed in the semiconductor layer, sandwiching the gate electrode.
As described above, in this aspect, after implanting the impurity into the semiconductor layer for forming the channel stopper region using the second masking layer as a mask, the third masking layer formed on the sidewall of the second masking layer as well as the second masking layer are used to pattern the semiconductor layer. Accordingly, it is possible to form a channel stopper region in the vicinity of the edge portion of the semiconductor layer in a self-aligned manner. After removing the second and third masking layers, a sidewall insulation layer is formed on the sidewall of the semiconductor layer. After the formation of this sidewall insulation layer, the first masking layer and insulation layer are etched away. At this time, formation of the sidewall insulation layer effectively prevents formation of a recess portion immediately under the edge portion of the semiconductor layer upon etching of the first masking layer and the insulation layer. Thus, it is possible to suppress the insulation breakdown of the gate insulation layer at the bottom portion of sidewall of the semiconductor layer effectively.
The above-described insulation layer is preferably a CVD (Chemical Vapor Deposition) oxide layer, the buried insulation layer is preferably an oxide layer formed by thermal oxidation, and the sidewall insulation layer is preferably a CVD (Chemical Vapor Deposition) oxide layer using TEOS (Tetra Ethyl Ortho Silicate). As described above, by providing a CVD oxide layer as the insulating layer, it is possible to reduce the time for wet etching as compared to the case in which an oxide layer formed by thermal oxidation is used. Accordingly, the amount of etching of the buried insulation layer caused by the etching of the insulation layer can be reduced. In addition, by providing CVD oxide layer using TEOS as the sidewall insulation layer, the etching rate of the sidewall insulation layer can be larger than the etching rate of the buried insulation layer. Accordingly, it is possible to prevent effectively the recess portion from being formed to extend under the sidewall insulation layer. As a result, patterning of the gate electrode would be easier as compared to the case in which the recess portion is formed to extend under the sidewall insulation layer.